Integrated circuit design and manufacturing are incredibly complex operations. A circuit design, which begins as a functional description of circuit logic, must be converted into circuit components, such as transistors, resistors, capacitors, and connecting wires, formed from areas of conductors, semiconductors, and insulators on a semiconductor silicon die. Each of the steps in converting from logic to physical circuit must be verified to ensure that it properly implements the designed logic.
The physical circuit does not behave like ideal, theoretical components so a design that works as a model may not work when produced as a physical device. For example, the capacitance between adjacent conductors affects the circuit operation, as does the time required for electronic signals to move between elements in the circuit. Extensive testing and analysis is performed as the circuit logic is converted into a circuit design and then into physical circuits.
As the capability of integrated circuits (IC) fabrication processes advance, the number of transistors and logic gates that can be applied on a semiconductor chip increases exponentially. Current integrated circuits include tens of million of logic gates on a single chip. Companies are taking advantage of the latest silicon processes by combining within a single chip all the functions of a traditional system, including processors, digital signal processors (DSP), memory, and peripheral interfaces.
Moore's law states the computational power of computers, which depends on the number of features in an integrated circuit, doubles every eighteen months. This doubling is due fabrication advances that shrink the size of circuit features. One consequence of decreased feature sizes is that there is an ever-increasing amount of space available on the silicon die that can be used for circuitry. It is critical that design time be keep low so that new products can be brought to market as quickly as possible so there is no additional time available to fill the space. While the productivity of circuit designed is estimated to be increasing at about twenty percent a year, this is insufficient to take advantage of the available space on the chips in time to meet the market demand.
The number of designers is not growing. Designers are not able to keep up with the increased capacity of the chips. For example, many semiconductor houses have the silicon process complexity to put more than 20 million logic gates on a chip. However, the average application specific integrated circuit (ASIC) today includes roughly 500 thousand gates. It is widely recognized that a productivity gap exists between the capabilities of today's electronic design automation (EDA) tools and the number of gates available on a single die in the current silicon processes.
To overcome this gap, designers seek to create multi-million gate system-on-chip (SoC) designs by reusing existing pre-verified design blocks, referred to as intellectual property (IP), in a block-based methodology.
In the electronics industry the value of design reuse has been well understood for a long time. Even with this understanding, limited design reuse has been occurring so far. One barrier to design reuse is the technical challenges involved in sharing IP between design groups. A design is more than a single file. A design typically comprises a multitude of parts in different formats and created and edited by different tools. Although some individual design groups have created standardized directory formats for different file types, there has been no standards across the industry or even across most companies. When a design is provided to another designer, there has been no standardization regarding how the files are named or organized, so it can be difficult to determine where all the necessary files are located.
To complicate matters, the productivity issue driving design reuse is not only a design creation gap. It is also a design verification gap. The widespread use of synthesis allows designers to automatically generate logic circuits or gates from a description of the logic operations that are to be performed. It is necessary to verify that the output of the synthesis step produces the required logical results.
As designs change over time, the different files that make up the design may be revised. The changes in individual files result in version changes to the files. It is difficult to keep track of all the different versions of the multiple files to keep track of what files are currently used in a design.
For groups of engineers sharing design data, there are also issues like incompatible tools and lack of communication. Information, such as the version of the tool creating certain of the design files are not maintained. If one designer tries to use a design created by another designer, the difference in tools or versions of tools may introduce errors in reprocessing the files. If the original designers are not available to explain the design files, it can be impractical to re-engineer a legacy block from one technology to the next, and may be prohibitive.
Beyond the technical barriers to design reuse, there are also very real economic barriers to the initial adoption of design reuse. For example, a design manager may find it difficult to justify designing a new block for reuse while trying to maintain the SoC design schedule. The extra work required to make the design reusable uses up limited resources and jeopardizes the existing project. At the same time, the existing design group may never reuse this block, making the choice of designing for reuse one of known risk for uncertain reward. This barrier can only be overcome when the time saved reusing existing blocks in an SoC design more than makes up for the effort required to design new blocks in a usable manner.
Other barriers to design reuse are cultural in nature. Every engineering organization has its own design culture. Many engineers in that culture will prefer to create rather than verify, innovate rather than re-engineer. Additionally, traditional company incentive programs tend to reward the designer for innovation. Design reuse, however, requires that design creation and innovation be moved up a level of abstraction.
Even within a given organization, designers attempting to reuse will find incompatible deliverable formats, mismatched block interfaces, incomplete documentation and inconsistent tool flows. Moreover, in many cases, there is no clear definition of what it means for a block to be reusable. To further complicate matters, the definition of “reusable” differs between designers, organizations and design requirements. Additionally, with growing chip complexity, functional verification is also a formidable barrier to design reuse. If a designer must be intimately familiar with the minutiae of a component in order to verify that block, then little time is saved in design reuse.